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Z86233/243 CP96DZ81201
CUSTOMER P ROCUREMENT S PECIFICA TION
Z86233/243
CMOS Z8(R) 8K ROM CONSUMER CONTROLLER PROCESSOR
FEATURES
Part ROM RAM Kbytes bytes 237 236 I/O 24 32 Package Information 28-pinDIP,SOIC,PLCC 40-pin DIP, 44-pin PLCC, 44-pin QFP
s
32 Input/Output Lines (Three with Comparator Inputs) (Z86243 Only) Vectored, Prioritized Interrupts with Programmable Polarity Two Comparators Two Programmable 8-Bit Counter/Timers, Each with a 6-Bit Programmable Prescaler Watch-Dog Timer (WDT)/Power-On Reset (POR) On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive RAM and ROM Protect Clock Free Watch-Dog Timer (WDT) Reset
Z86233 8 Z86243 8
s
s s
s
s
3.0-to 5.5-Volt Operating Range Low-Power Consumption: 40 mW (Typical @5.0V) 0C to +70C Temperature Range (-40C to +105C Temperature Range Available) Three Expanded Register File Control Registers Z86C33/C43 Pin and Package Compatible Version (With Addition of 4K ROM)
s s
s
s s
s s
GENERAL DESCRIPTION
The Z86233/243 Consumer Controller Processor is a member of Zilog's Z8(R) single-chip microcontroller family featuring enhanced wake-up circuitry, programmable Watch-Dog timers and low-EMI options. The parts provide flexible and efficient growth paths for designers currently using the 4K ROM versions of the consumer controller devices (Z86C30/C40/C33/C43). Four address spaces, the Program Memory, Register File, Data Memory and Expanded Register File (ERF), support a wide range of memory configurations. Through the ERF, the designer has access to two additional control registers which provide extra peripheral devices, I/O ports, and register addresses. For applications demanding powerful I/O capabilities, the Z86243 provides 32 pins dedicated to input and output. The Z86233 provides 24 pins dedicated to input and output. These lines are grouped into four ports with eight lines each, and are configurable under software control to provide timing, status signals, or parallel I/O. With ROM/ROMless selectivity, the Z86243 provides both external memory and pre-programmed ROM, which enables this Z8 microcontroller to be used in high-volume applications, or where code flexibility is required. Note: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP96DZ81201 (8/96)
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GENERAL DESCRIPTION (Continued)
Output Input Vcc GND * * * * XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT POR ,
R//RL
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File ERF
Prg. Memory 8192 Bytes
Two Analog Comparators
Program Counter
Port 2
Port 0
Port 1 *
4 I/O (Bit Programmable)
4
8 Address/Data or I/O (Byte Programmable) * Not available on Z86233. Available on Z86243 44-Pin QFP and PLCC versions only.
Address or I/O (Nibble Programmable)
Functional Block Diagram
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PIN DESCRIPTION
28-Pin DIP/SOIC/PLCC Pin Identification Pin # 1-3 4-7 8 9 10 11-13 14-15 16 17 18 19-21 22 23 24-28 Symbol P25-P27 P07-P04 VCC XTAL2 XTAL1 P33-P31 P35-P34 P37 P36 P30 P02-P00 GND P03 P24-P20 Function Port 2, Pins 5,6,7 Port 0, Pins 4,5,6,7 Power Supply Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Direction In/Output In/Output Output Input Fixed Input Fixed Output Fixed Output Fixed Output
P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 Z86233 22 21 20 19 18 17 16 15
P24 P23 P22 P21 P20 P03 GND P02 P01 P00 P30 P36 P37 P35
Port 3, Pin 0 Fixed Input Port 0, Pins 0,1,2 In/Output Ground Port 0, Pins 3 In/Output Port 2, Pins 0,1,2,3,4 In/Output
28-Pin DIP Pin Configuration
P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Z86233
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P24 P23 P22 P21 P20 P03 GND P02 P01 P00 P30 P36 P37 P35
4 P05 XXX P06 XXX P07 XXX VCC XXX XT2 XXX XT1 XXX P31 XXX 5
P04 P27 P26
P25 P24 P23 P22
1
26 25
Z86233
11 12
P32 P33 P34
19 18
P35 P37 P36 P30
P21 XXX P20 XXX P03 XXX GND XXX P02 XXX P01 XXX P00 XXX
28-Pin SOIC Pin Configuration
28-Pin PLCC Pin Configuration
CP96DZ81201 (8/96)
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PIN DESCRIPTION (Continued)
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Z86243 DIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET
40-Pin DIP Pin Configuration
40-Pin DIP Pin Configuaration Pin # 1 2-4 5-7 8-9 10 11 12-13 14 15 16-18 19 20 21 Symbol R//W P25-P27 P04-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS /RESET Function Read/Write Port 2, Pins 5, 6, 7 Port 0, Pins 4, 5, 6 Port 1, Pins 4, 5 Port 0, Pin 7 Power Supply Port 1, Pins 6, 7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1, 2, 3 Port 3, Pin 4 Address Strobe Reset Direction Output In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output Input Pin # 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40 Symbol P35 P37 P36 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-P24 /DS Function Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2, 3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe Direction Output Output Output Input In/Output In/Output In/Output In/Output In/Output In/Output Output
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GND GND
P20
P03
P13
P12
P02
P10
P01
6 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Z86243 PLCC
P00
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28
VCC
VCC
P11
44-Pin PLCC Pin Configuration
44-Pin PLCC Pin Identification Pin # 1 2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23 24 25-26 Symbol GND GND P12-P13 P03 P20-P24 /DS N/C R//W P25-P27 P04-P06 P14-P15 P07 VCC VCC P16-P17 Function Direction Pin # 27 28 29-31 32 33 34 35 36 37 38 39 40-41 42-43 44 Symbol XTAL2 XTAL1 P31-P33 P34 /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 Function Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Direction Output Input Input Output Output Input Input Output Output Output Input In/Output In/Output In/Output
Ground Ground Port 1, Pins 2,3 In/Output Port 0, Pin 3 In/Output Port 2, Pins 0,1,2,3,4 In/Output Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Power Supply Port 1, Pins 6,7 Output Output In/Output In/Output In/Output In/Output
In/Output
CP96DZ81201 (8/96)
XTAL2
XTAL1
P05
P06
P14
P15
P07
P16
P17
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Z86233/243 CP96DZ81201
PIN DESCRIPTION (Continued)
GND GND P20 P03 P13 P12 P02 P10 P01 P00 22 21 20 19 P11
33 32 31 30 29 28 27 26 25 24 23 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Z86243 QFP
18 17 16 15 14 13 12
44-Pin QFP Pin Configuration
44-Pin QFP Pin Identification Pin # 1-2 3-4 5 6-7 8-9 10 11 12-14 15 16 17 18 19 20 Symbol P05-P06 P14-P05 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS R//RL /RESET P35 P37 Function Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Direction In/Output In/Output In/Output In/Output Output Input Input Output Output Input Input Output Output Pin # 21 22 23-24 25-26 27 28 29 30-31 32 33-37 38 39 40 41-43 44 Symbol P36 P30 P00-P01 P10-P11 P02 GND GND P12-P13 P03 P20-24 /DS N/C R//W P25-P27 P04 Function Port 3, Pin 6 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Direction Output Input In/Output In/Output In/Output
XTAL2
XTAL1
VCC
VCC
P05
P06
P14
P15
P07
P16
P17
In/Output In/Output In/Output Output Output In/Output In/Output
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin
Notes: [1] This applies to all pins except XTAL pins and where otherwise noted. [2] There is no input protection diode from pin to VDD. [3] This excludes XTAL pins. [4] Device pin is not at an output Low state.
Min -40 -65 -0.6 -0.3 -0.6
Max +105 +150 +7 +7 VDD+1 1.21 220 180 +600 +600 25 25
Units C C V V V W mA mA A A mA mA
-600 -600
Notice: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD - (sum of IOH) ] + sum of [ (VDD - VOH) x IOH ] + sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load).
From Output Under Test
150 pF
Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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DC ELECTRICAL CHARACTERISTICS
TA = 0 C to +70C Min Max 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 TA = -40C to +105C Typical [1] Min Max @ 25C Units Conditions 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 1.8 2.6 1.2 2.1 1.8 2.6 1.1 1.6 3.1 4.8 0.2 0.1 0.3 0.4 1.8 2.6 1.1 1.6 0.3 0.2 10 10 0.004 0.004 0.004 0.004 -60 -85 7 20 5 15 2.0 3.7 1.5 2.9 2 4 310 600 V V V V V V V V V V V V V V V V V V V V mV mV A A A A A A mA mA mA mA mA mA mA mA A A A A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Sym Parameter VCH VCL VIH VIL VOH1 VOL1 VOL2 VRH VRl VOLR
VCC Note [3]
Notes
Clock Input High Voltage 3.0V 5.5V Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.6 0.6 25 25 1 1 1 1 -130 -180 20 25 15 20 4.5 8 3.4 7.0 8 10 500 800
GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.6 0.6 25 25 2 2 2 2 -130 -180 20 25 15 20 4.5 8 3.4 7.0 8 10 600 1000
IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA IOL = +12 mA
[8] [8] [8] [8] [8] [8] [13] [13] [13] [13] [13] [13] [10] [10]
Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
IOL = +1.0 mA IOL = +1.0 mA
VOFFSET Comparator Input Offset Voltage IIL Input Leakage IOL IIR ICC Output Leakage Reset Input Current Supply Current
-1 -1 -1 -1 -20 -20
-1 -1 -1 -1 -18 -18
VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
@ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz VIN = OV, VCC @ 16 MHz VIN = OV, VCC @ 16 MHz Clock Divide-by-16 @ 16 MHz Clock Divide-by-16 @ 16 MHz
[4] [4] [4] [4] [4] [4] [4] [4]
ICC1
Standby Current (Halt Mode)
ICC2
Standby Current (Stop Mode)
VIN = OV, VCC WDT is not Running [6,11] VIN = OV, VCC WDT is not Running [6,11] VIN = OV, VCC WDT is Running [6,11,14] VIN = OV, VCC WDT is Running [6,11,14]
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DC ELECTRICAL CHARACTERISTICS (Continued)
TA = 0 C to +70C Min Max TA = -40C to +105C Min Max
Sym Parameter VICR IALL IALH VLV VOH VOL Input Common Mode Voltage Range Auto Latch Low Current Auto Latch High Current VCC Low Voltage Protection Voltage Output High Voltage (Low EMI Mode) Output Low Voltage (Low EMI Mode)
VCC Note [3] 3.0 5.5 3.0V 5.5V 3.0V 5.5V
Typical [1] @ 25C Units V V 3 5 -3 -6 2.8 2.8 3.1 4.8 A A A A V V V V V
Conditions
Notes [10] [10]
GND-0.3 VCC-1.0V GND-0.3 VCC-1.5V GND-0.3 VCC-1.0V GND-0.3 VCC-1.5V 8 15 -5 -8 2.1 2.4 3.1 VCC-0.4 VCC-0.4 0.6 0.4 0.6 0.4 10 20 -7 -10 3.3
OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC 4 MHz max Int. CLK Freq. 6 MHz max Int. CLK Freq. IOH = -0.5 mA IOH = -0.5 mA IOL = 1.0 mA IOL = 1.0 mA
[9] [9] [9] [9] [7,15] [7,14]
3.3V 5.0V 3.3V 5.0V
VCC-0.4 VCC-0.4
0.2 0.1
Notes: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND = 0V. [3] The VDD voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Standard Mode (not Low EMI). [9] Auto Latch (Mask Option) selected. [10] For analog comparator, inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating. [12] Excludes clock pins. [13] Z86243 Only. [14] 0C to 70C (standard temperature). [14] -40C to 105C (extended temperature).
CP96DZ81201 (8/96)
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AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram
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AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (SCLK/TCLK = XTAL/2)
TA = 0C to +70C Note [3] 12 MHz 16 MHz VCC Min Max Min Max 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 35 35 45 45 250 250 55 55 0 0 200 200 110 110 150 150 0 0 45 55 30 45 45 45 45 45 55 55 45 55 310 310 65 65 115 75 35 35 45 45 60 60 30 30 0 0 50 50 35 35 25 25 35 35 25 25 35 35 230 230 65 65 115 75 35 35 40 40 0 0 135 135 80 80 75 75 0 0 45 55 30 45 45 45 45 45 55 55 45 55 310 310 45 45 60 60 30 30 25 25 35 35 180 180 55 55 0 0 200 200 110 110 150 150 0 0 50 50 35 55 25 25 35 35 25 25 35 35 230 230 TA = -40C to +105C 12 MHz 16 MHz Min Max Min Max 35 35 45 45 250 250 40 40 0 0 135 135 80 80 75 75 25 25 35 35 180 180
No Symbol 1 2 3 4 5 6 7 8 9 TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS)
Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid
Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [2] [2] [1,2] [2]
[1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [2] [2] [1,2] [2] [1,2] [2]
10 TdDS(A) 11 TdDS(AS) 12 TdR/W(AS) 13 TdDS(R/W)
3.0 5.5 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 5.5 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) 18 TdDI(DS) 19 TdDM(AS) /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Rise Delay 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] The VDD voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
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AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
1 1
Stop-Mode Recovery Source
10
Additional Timing
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AC ELECTRICAL CHARACTERISTICS Additional Timing Table (SCLK/TCLK = XTAL/2)
TA = 0C to +70C 12 MHz 16 MHz Min Max Min Max 83 83 DC DC 15 15 62.5 62.5 DC DC 15 15 TA = -40C to +105C 12 MHz 16 MHz Min Max Min Max Units 83 83 DC DC 15 15 62.5 62.5 DC DC 15 15 ns ns ns ns ns ns ns ns
No Symbol Parameter 1 2 3 4 5 6 7 TpC Input Clock Period
VCC Note[6] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]
TrC,TfC Clock Input Rise & Fall Times TwC TwTinL Input Clock Width Timer Input Low Width
41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80 7 3 24 13
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80 7 3 24 13
41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80 7 3 25 14
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80 7 3 25 14
TwTinH Timer Input High Width TpTin Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time
TrTin, TfTin 8A TwIL 8B TwIL 9 TwIH
ns ns ns ns
[1] [1] [1,2] [1,2] [1,3] [1,3] [1,2] [1,2]
10 Twsm 11 Tost 12 Twdt
STOP-Mode Recovery Width Spec 3.0V 5.5V Oscillator Startup Time 3.0V 5.5V Watch-Dog Timer Delay Time Before Time-Out 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
ns ns [4] [4] ms ms ms ms ms ms ms ms ms ms D1 0 0 0 0 1 1 1 1 D0 0 [5] 0 [5] 1 [5] 1 [5] 0 [5] 0 [5] 1 [5] 1 [5]
13 TPOR
Power On Reset Delay
Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 0. [5] Reg. WDTMR, internal RC used. [6] The VDD voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
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AC ELECTRICAL CHARACTERISTICS Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL)
TA = 0C to +70C 4 MHz Min Max 250 250 DC DC 25 25 TA = -40C to +105C 4 MHz Min Max Units 250 250 DC DC 25 25 ns ns ns ns ns ns ns ns
No 1 2 3 4 5 6 7 8A 8B 9 10 11
Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TfTin TwIL TwIL TwIH Twsm Tost
Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time STOP-Mode Recovery Width Spec Oscillator Startup Time
Vcc Note [6] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Notes [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8]
125 125 100 70 3TpC 3TpC 4TpC 4TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 5TpC 5TpC
125 125 100 70 3TpC 3TpC 4TpC 4TpC 100 100 100 70 3TpC 3TpC 3TpC 2TpC 12 12 5TpC 5TpC
ns ns ns ns
[1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8]
ns ns
[4,8] [4,8] [4,8,9] [4,8,9]
Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P33-P31). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP mode delay is on. [5] Reg. WDTMR. [6] The VDD voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.5V 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver.
14
CP96DZ81201 (8/96)
Z86233/243 CP96DZ81201
AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1 3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
CP96DZ81201 (8/96)
15
Z86233/243 CP96DZ81201
AC ELECTRICAL CHARACTERISTICS Handshake Timing Table
TA = 0C to +70C 12 MHz 16 MHz Min Max Min Max 0 0 160 115 155 110 160 115 120 80 0 0 42 42 0 0 160 115 110 80 110 80 110 80 110 80 0 0 31 31 0 0 160 115 110 80 110 80 0 0 160 115 155 110 160 115 120 80 0 0 42 42 0 0 160 115 110 80 110 80 TA = -40C to +105C 12 MHz 16 MHz Min Max Min Max 0 0 160 115 155 110 160 115 120 80 0 0 31 31 0 0 160 115 0 0 160 115 155 110 160 115 120 80
No Symbol 1 2 3 4 5 6 7 8 9 TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV)
Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay
VCC Note[1,2] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
10 TwRDY 11 TdRDY0d(DAV)
Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] The VDD voltage specification of 3.0V guarantees 3.3V 0.3V and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
16
CP96DZ81201 (8/96)
Z86233/243 CP96DZ81201
PRECAUTIONS
(1) When in ROM Protect Mode, and executing out of External Program Memory , instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in ROM Protect Mode, and executing out of Internal Program Memory , instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. (2) The device has an oscillator-free reset for the device pins. When the device is reset from a WDT timeout, POR, or VBO, the reset will force the device pins to their reset default state even if the oscillator is not running. (3) The Port 3 outputs are reset to High State after Reset, except after Stop-Mode Recovery, at which the outputs remain in the last state. (4) Extended timing is operable. (5) P0/P1/P2/P3 is Low-EMI software programmable. (6) P0/P1/P2 is software programmable for open-drain. (7) Expanded register PCON is Write Only. (8) WDTMR is writeable only within the first 60 internal system clocks after Reset. Afterward, the WDTMR is write protected. (9) Device functions down to the VLV threshold. At temperatures less than 25C, the VLV threshold will rise to a maximum VDD of 3.6V. (10) Low EMI is 25 percent of standard pull-down output driver and 25 percent of standard pull-up output driver. (11) There is no clock filter on Reset pin. (12) Registers FE Hex (SPH) and FF Hex (SPL) are set to 00Hex after any reset. (13) When Low EMI OSC is selscted (PCONReg Bit D7=0), the output drive of /DS, /AS, and R//W will also be in low emi mode. (14) P01M Reg Bit D4,D3 must be set to 00Hex for Z86233.
CP96DZ81201 (8/96)
17
Z86233/243 CP96DZ81201
(c) 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
18
CP96DZ81201 (8/96)

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